NAME=load doubleword byte-reverse indexed ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi 7c006428)
EOF
EXPECT=<<EOF
ldbrx r0, 0, r12
0x00000000 r12,[1],8,1,r12,+,[1],<<,|,16,2,r12,+,[1],<<,|,24,3,r12,+,[1],<<,|,32,4,r12,+,[1],<<,|,40,5,r12,+,[1],<<,|,48,6,r12,+,[1],<<,|,56,7,r12,+,[1],<<,|,r0,=
EOF
RUN

NAME=store doubleword byte-reverse indexed ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi 7c006528)
EOF
EXPECT=<<EOF
stdbrx r0, 0, r12
0x00000000 0xff,r0,&,r12,=[1],8,r0,>>,0xff,&,1,r12,+,=[1],16,r0,>>,0xff,&,2,r12,+,=[1],24,r0,>>,0xff,&,3,r12,+,=[1],32,r0,>>,0xff,&,4,r12,+,=[1],40,r0,>>,0xff,&,5,r12,+,=[1],48,r0,>>,0xff,&,6,r12,+,=[1],56,r0,>>,0xff,&,7,r12,+,=[1]
EOF
RUN

NAME=ldbrx byte-reverse emulation ppc-64
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 0123456789abcdef @ 0x100
wx 7c006428 @ 0
aei
aeim
ar r12=0x100
aes
ar r0
EOF
EXPECT=<<EOF
0xefcdab8967452301
EOF
RUN

NAME=isel selects rA when eq condition bit set ppc-64
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c64289e @ 0
aei
aeim
ar r4=0x11
ar r5=0x22
ar cr0=0
aes
ar r3
EOF
EXPECT=<<EOF
0x00000011
EOF
RUN

NAME=isel selects rB when eq condition bit clear ppc-64
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c64289e @ 0
aei
aeim
ar r4=0x11
ar r5=0x22
ar cr0=0x40
aes
ar r3
EOF
EXPECT=<<EOF
0x00000022
EOF
RUN

NAME=isel selects rA when lt condition bit set ppc-64
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c64281e @ 0
aei
aeim
ar r4=0x11
ar r5=0x22
ar cr0=0x80
aes
ar r3
EOF
EXPECT=<<EOF
0x00000011
EOF
RUN

NAME=isel selects rA when gt condition true ppc-64
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c64285e @ 0
aei
aeim
ar r4=0x11
ar r5=0x22
ar cr0=0x10
aes
ar r3
EOF
EXPECT=<<EOF
0x00000011
EOF
RUN

NAME=isel gt condition is false on equality ppc-64
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c64285e @ 0
aei
aeim
ar r4=0x11
ar r5=0x22
ar cr0=0
aes
ar r3
EOF
EXPECT=<<EOF
0x00000022
EOF
RUN

NAME=isel uses literal zero for rA field r0 ppc-64
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c604f9e @ 0
aei
aeim
ar r9=0x99
ar cr7=0
aes
ar r3
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=unsigned modulo doubleword ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi 7c642a12)
EOF
EXPECT=<<EOF
modud r3, r4, r5
0x00000000 r5,r4,%,r3,=
EOF
RUN

NAME=unsigned modulo doubleword emulates ppc-64
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c642a12 @ 0
aei
aeim
ar r4=17
ar r5=5
aes
ar r3
EOF
EXPECT=<<EOF
0x00000002
EOF
RUN

NAME=signed modulo doubleword emulates ppc-64
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c642e12 @ 0
aei
aeim
ar r4=0xffffffffffffffef
ar r5=5
aes
ar r3
EOF
EXPECT=<<EOF
0xfffffffffffffffe
EOF
RUN

NAME=rotate left doubleword emulates ppc-64
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 78832810 @ 0
aei
aeim
ar r4=0x8000000000000001
ar r5=1
aes
ar r3
EOF
EXPECT=<<EOF
0x00000003
EOF
RUN

NAME=fadd esil string ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi fc22182a)
EOF
EXPECT=<<EOF
fadd f1, f2, f3
0x00000000 f3,f2,F+,f1,=
EOF
RUN

NAME=fadds single precision esil string ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi ec22182a)
EOF
EXPECT=<<EOF
fadds f1, f2, f3
0x00000000 32,DUP,f3,f2,F+,D2F,F2D,f1,=
EOF
RUN

NAME=fmadd esil string ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi fc2220fa)
EOF
EXPECT=<<EOF
fmadd f1, f2, f3, f4
0x00000000 f4,f3,f2,F*,F+,f1,=
EOF
RUN

NAME=fcmpu esil string ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi fc021800)
EOF
EXPECT=<<EOF
fcmpu cr0, f2, f3
0x00000000 0x80,f3,f2,F<,*,f2,f3,F<,+,cr0,=
EOF
RUN

NAME=fmr/fneg/fabs sign esil strings ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi fc201090)
.(pi fc201050)
.(pi fc201210)
EOF
EXPECT=<<EOF
fmr f1, f2
0x00000000 f2,f1,=
fneg f1, f2
0x00000000 0x8000000000000000,f2,^,f1,=
fabs f1, f2
0x00000000 0x7fffffffffffffff,f2,&,f1,=
EOF
RUN

NAME=lfd/lfs/stfd/stfs esil strings ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi c8230010)
.(pi c0230010)
.(pi d8230010)
.(pi d0230010)
EOF
EXPECT=<<EOF
lfd f1, 0x10(r3)
0x00000000 16,r3,+,[8],f1,=
lfs f1, 0x10(r3)
0x00000000 32,16,r3,+,[4],F2D,f1,=
stfd f1, 0x10(r3)
0x00000000 f1,16,r3,+,=[8]
stfs f1, 0x10(r3)
0x00000000 32,f1,D2F,16,r3,+,=[4]
EOF
RUN

NAME=fsub emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc221828 @ 0
aei
ar f2=0x4010000000000000
ar f3=0x3ff8000000000000
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x4004000000000000
EOF
RUN

NAME=fdiv emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc221824 @ 0
aei
ar f2=0x4008000000000000
ar f3=0x4000000000000000
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x3ff8000000000000
EOF
RUN

NAME=fadds single rounding emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx ec22182a @ 0
aei
ar f2=0x3ff199999999999a
ar f3=0x400199999999999a
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x400a666660000000
EOF
RUN

NAME=fmadd emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc2220fa @ 0
aei
ar f2=0x4000000000000000
ar f3=0x4008000000000000
ar f4=0x3ff0000000000000
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x401c000000000000
EOF
RUN

NAME=fcfid int to double emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc20169c @ 0
aei
ar f2=5
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x4014000000000000
EOF
RUN

NAME=fctidz double to int emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc20165e @ 0
aei
ar f2=0x4004000000000000
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x00000002
EOF
RUN

NAME=fcmpu sets cr byte lt/gt/eq emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc021800 @ 0
aei
ar f2=0x3ff0000000000000
ar f3=0x4000000000000000
aepc 0
aes
ar cr0
ar f2=0x4000000000000000
ar f3=0x3ff0000000000000
aepc 0
aes
ar cr0
ar f3=0x4000000000000000
aepc 0
aes
ar cr0
EOF
EXPECT=<<EOF
0x00000080
0x00000001
0x00000000
EOF
RUN

NAME=stfd then lfd roundtrip emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
aei
aeim
ar r3=0
ar f1=0x4004000000000000
wx d8230020 @ 0
aepc 0
aes
wx c8a30020 @ 0
aepc 0
aes
ar f5
EOF
EXPECT=<<EOF
0x4004000000000000
EOF
RUN

NAME=fp single-precision arith esil strings ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi ec221828)
.(pi ec2200f2)
.(pi ec221824)
.(pi fc20102c)
.(pi ec20102c)
EOF
EXPECT=<<EOF
fsubs f1, f2, f3
0x00000000 32,DUP,f3,f2,F-,D2F,F2D,f1,=
fmuls f1, f2, f3
0x00000000 32,DUP,f3,f2,F*,D2F,F2D,f1,=
fdivs f1, f2, f3
0x00000000 32,DUP,f3,f2,F/,D2F,F2D,f1,=
fsqrt f1, f2
0x00000000 f2,SQRT,f1,=
fsqrts f1, f2
0x00000000 32,DUP,f2,SQRT,D2F,F2D,f1,=
EOF
RUN

NAME=fma family esil strings ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi ec2220fa)
.(pi fc2220f8)
.(pi ec2220f8)
.(pi fc2220fe)
.(pi ec2220fe)
.(pi fc2220fc)
.(pi ec2220fc)
EOF
EXPECT=<<EOF
fmadds f1, f2, f3, f4
0x00000000 32,DUP,f4,f3,f2,F*,F+,D2F,F2D,f1,=
fmsub f1, f2, f3, f4
0x00000000 f4,f3,f2,F*,F-,f1,=
fmsubs f1, f2, f3, f4
0x00000000 32,DUP,f4,f3,f2,F*,F-,D2F,F2D,f1,=
fnmadd f1, f2, f3, f4
0x00000000 f4,f3,f2,F*,F+,-F,f1,=
fnmadds f1, f2, f3, f4
0x00000000 32,DUP,f4,f3,f2,F*,F+,-F,D2F,F2D,f1,=
fnmsub f1, f2, f3, f4
0x00000000 f4,f3,f2,F*,F-,-F,f1,=
fnmsubs f1, f2, f3, f4
0x00000000 32,DUP,f4,f3,f2,F*,F-,-F,D2F,F2D,f1,=
EOF
RUN

NAME=fnabs/fcpsgn esil strings ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi fc201110)
.(pi fc221810)
EOF
EXPECT=<<EOF
fnabs f1, f2
0x00000000 0x8000000000000000,f2,|,f1,=
fcpsgn f1, f2, f3
0x00000000 0x8000000000000000,f2,&,0x7fffffffffffffff,f3,&,|,f1,=
EOF
RUN

NAME=fp convert esil strings ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi fc20179c)
.(pi ec20169c)
.(pi ec20179c)
.(pi fc20165c)
.(pi fc201018)
.(pi fc2013d0)
.(pi fc201390)
.(pi fc201310)
.(pi fc201350)
EOF
EXPECT=<<EOF
fcfidu f1, f2
0x00000000 f2,U2D,f1,=
fcfids f1, f2
0x00000000 32,DUP,f2,I2D,D2F,F2D,f1,=
fcfidus f1, f2
0x00000000 32,DUP,f2,U2D,D2F,F2D,f1,=
fctid f1, f2
0x00000000 f2,D2I,f1,=
frsp f1, f2
0x00000000 32,DUP,f2,D2F,F2D,f1,=
frim f1, f2
0x00000000 f2,FLOOR,f1,=
frip f1, f2
0x00000000 f2,CEIL,f1,=
frin f1, f2
0x00000000 f2,ROUND,f1,=
friz f1, f2
0x00000000 f2,D2I,I2D,f1,=
EOF
RUN

NAME=fp indexed and update load/store esil strings ppc-64
FILE=-
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
(pi bytes;wx $0;pi 1;pie 1)
.(pi cc230010)
.(pi 7c2324ae)
.(pi 7c2324ee)
.(pi c4230010)
.(pi 7c23242e)
.(pi 7c23246e)
.(pi dc230010)
.(pi 7c2325ae)
.(pi 7c2325ee)
.(pi d4230010)
.(pi 7c23252e)
.(pi 7c23256e)
.(pi 7c201eae)
.(pi 7c201eee)
.(pi 7c201fae)
EOF
EXPECT=<<EOF
lfdu f1, 0x10(r3)
0x00000000 16,r3,+,[8],f1,=,16,r3,+=
lfdx f1, r3, r4
0x00000000 r3,r4,+,[8],f1,=
lfdux f1, r3, r4
0x00000000 r3,r4,+,[8],f1,=,r3,r4,+,r3,=
lfsu f1, 0x10(r3)
0x00000000 32,16,r3,+,[4],F2D,f1,=,16,r3,+=
lfsx f1, r3, r4
0x00000000 32,r3,r4,+,[4],F2D,f1,=
lfsux f1, r3, r4
0x00000000 32,r3,r4,+,[4],F2D,f1,=,r3,r4,+,r3,=
stfdu f1, 0x10(r3)
0x00000000 f1,16,r3,+,=[8],16,r3,+=
stfdx f1, r3, r4
0x00000000 f1,r3,r4,+,=[8]
stfdux f1, r3, r4
0x00000000 f1,r3,r4,+,=[8],r3,r4,+,r3,=
stfsu f1, 0x10(r3)
0x00000000 32,f1,D2F,16,r3,+,=[4],16,r3,+=
stfsx f1, r3, r4
0x00000000 32,f1,D2F,r3,r4,+,=[4]
stfsux f1, r3, r4
0x00000000 32,f1,D2F,r3,r4,+,=[4],r3,r4,+,r3,=
lfiwax f1, 0, r3
0x00000000 r3,[4],f1,=
lfiwzx f1, 0, r3
0x00000000 r3,[4],f1,=
stfiwx f1, 0, r3
0x00000000 f1,r3,=[4]
EOF
RUN

NAME=fsqrt emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc20102c @ 0
aei
ar f2=0x4030000000000000
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x4010000000000000
EOF
RUN

NAME=fmsub emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc2220f8 @ 0
aei
ar f2=0x4000000000000000
ar f3=0x4008000000000000
ar f4=0x3ff0000000000000
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x4014000000000000
EOF
RUN

NAME=fnmadd negate emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc2220fe @ 0
aei
ar f2=0x4000000000000000
ar f3=0x4008000000000000
ar f4=0x3ff0000000000000
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0xc01c000000000000
EOF
RUN

NAME=fnabs emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc201110 @ 0
aei
ar f2=0x4004000000000000
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0xc004000000000000
EOF
RUN

NAME=fcpsgn emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc221810 @ 0
aei
ar f2=0xbff0000000000000
ar f3=0x4004000000000000
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0xc004000000000000
EOF
RUN

NAME=fcfidu unsigned int to double emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc20179c @ 0
aei
ar f2=0xffffffffffffffff
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x43f0000000000000
EOF
RUN

NAME=frsp round to single emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx fc201018 @ 0
aei
ar f2=0x400921fb54442d18
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x400921fb60000000
EOF
RUN

NAME=frim/frip/frin/friz rounding emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
aei
ar f2=0x4004000000000000
wx fc2013d0 @ 0
aepc 0
aes
ar f1
wx fc201390 @ 0
aepc 0
aes
ar f1
wx fc201310 @ 0
aepc 0
aes
ar f1
ar f2=0x4007333333333333
wx fc201350 @ 0
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x4000000000000000
0x4008000000000000
0x4008000000000000
0x4000000000000000
EOF
RUN

NAME=fsubs single rounding emulation ppc-64
FILE=malloc://0x40
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx ec221828 @ 0
aei
ar f2=0x4010000000000000
ar f3=0x3ff199999999999a
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x4007333340000000
EOF
RUN

NAME=lfdux indexed load with base update emulation ppc-64
FILE=malloc://0x80
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 4004000000000000 @ 0x20
wx 7c2324ee @ 0
aei
aeim
ar r3=0x10
ar r4=0x10
aepc 0
aes
ar f1
ar r3
EOF
EXPECT=<<EOF
0x4004000000000000
0x00000020
EOF
RUN

NAME=stfdux indexed store with base update emulation ppc-64
FILE=malloc://0x80
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c2325ee @ 0
wx c8a30000 @ 4
aei
aeim
ar f1=0x4004000000000000
ar r3=0x10
ar r4=0x10
aepc 0
aes
aes
ar f5
ar r3
EOF
EXPECT=<<EOF
0x4004000000000000
0x00000020
EOF
RUN

NAME=lfiwzx integer load to fpr emulation ppc-64
FILE=malloc://0x80
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 00000005 @ 0x20
wx 7c201eee @ 0
aei
aeim
ar r3=0x20
aepc 0
aes
ar f1
EOF
EXPECT=<<EOF
0x00000005
EOF
RUN

NAME=stfiwx integer store roundtrip emulation ppc-64
FILE=malloc://0x80
CMDS=<<EOF
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c201fae @ 0
wx 7ca01eee @ 4
aei
aeim
ar f1=0x1122334455667788
ar r3=0x20
aepc 0
aes
aes
ar f5
EOF
EXPECT=<<EOF
0x55667788
EOF
RUN

NAME=lwzx indexed load uses both base and index registers ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 1122334455667788 @ 0x108
wx 7c85302e @ 0
aei
aeim
ar r5=0x100
ar r6=8
aes
ar r4
EOF2
EXPECT=<<EOF2
0x11223344
EOF2
RUN

NAME=lwzx esil string adds index register ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c85302e @ 0
aoj 1 @ 0~{[0].esil}
EOF2
EXPECT=<<EOF2
r5,r6,+,[4],r4,=
EOF2
RUN

NAME=ldx indexed load full doubleword ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 1122334455667788 @ 0x108
wx 7c85302a @ 0
aei
aeim
ar r5=0x100
ar r6=8
aes
ar r4
EOF2
EXPECT=<<EOF2
0x1122334455667788
EOF2
RUN

NAME=lhzux indexed load with update writes back effective address ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 1122334455667788 @ 0x108
wx 7c85326e @ 0
aei
aeim
ar r5=0x100
ar r6=8
aes
ar r4
ar r5
EOF2
EXPECT=<<EOF2
0x00001122
0x00000108
EOF2
RUN

NAME=stwx indexed store uses both base and index registers ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c85312e @ 0
aei
aeim
ar r4=0xaabbccddeeff0011
ar r5=0x100
ar r6=8
aes
pv4 @ 0x108
EOF2
EXPECT=<<EOF2
0xeeff0011
EOF2
RUN

NAME=stbux indexed store with update writes byte and updates base ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c8531ee @ 0
aei
aeim
ar r4=0xaabbccddeeff0011
ar r5=0x100
ar r6=8
aes
pv1 @ 0x108
ar r5
EOF2
EXPECT=<<EOF2
0x11
0x00000108
EOF2
RUN

NAME=slw word shift left zero-extends to 32 bits ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7ca43030 @ 0
aei
aeim
ar r5=0xfffffffffffffff0
ar r6=4
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0xffffff00
EOF2
RUN

NAME=srw word shift right is 32-bit logical ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7ca43430 @ 0
aei
aeim
ar r5=0xfffffffffffffff0
ar r6=4
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x0fffffff
EOF2
RUN

NAME=rlwinm rotates the low 32 bits not the full register ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 54a4183e @ 0
aei
aeim
ar r5=0xfffffffffffffff0
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0xffffff87
EOF2
RUN

NAME=divw is a 32-bit signed divide ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c8533d6 @ 0
aei
aeim
ar r5=0xfffffffffffffff0
ar r6=7
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0xfffffffe
EOF2
RUN

NAME=divwu is a 32-bit unsigned divide ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c853396 @ 0
aei
aeim
ar r5=0xfffffffffffffff0
ar r6=7
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x24924922
EOF2
RUN

NAME=divd is a 64-bit signed divide ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c8533d2 @ 0
aei
aeim
ar r5=0xfffffffffffffff0
ar r6=7
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0xfffffffffffffffe
EOF2
RUN

NAME=lbzx byte indexed load ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 1122334455667788 @ 0x108
wx 7c8530ae @ 0
aei
aeim
ar r5=0x100
ar r6=8
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x00000011
EOF2
RUN

NAME=ldux doubleword indexed load with update ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 1122334455667788 @ 0x108
wx 7c85306a @ 0
aei
aeim
ar r5=0x100
ar r6=8
ar pc=0
s 0
aes
ar r4
ar r5
EOF2
EXPECT=<<EOF2
0x1122334455667788
0x00000108
EOF2
RUN

NAME=stdux doubleword indexed store with update ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c85316a @ 0
aei
aeim
ar r4=0xaabbccddeeff0011
ar r5=0x100
ar r6=8
ar pc=0
s 0
aes
pv8 @ 0x108
ar r5
EOF2
EXPECT=<<EOF2
0xaabbccddeeff0011
0x00000108
EOF2
RUN

NAME=lwax algebraic indexed load uses both base and index ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 1122334455667788 @ 0x108
wx 7c8532aa @ 0
aei
aeim
ar r5=0x100
ar r6=8
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x11223344
EOF2
RUN

NAME=sld doubleword shift left is 64-bit ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7ca43036 @ 0
aei
aeim
ar r5=0x8000000000000003
ar r6=4
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x00000030
EOF2
RUN

NAME=srd doubleword shift right is 64-bit logical ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7ca43436 @ 0
aei
aeim
ar r5=0x8000000000000003
ar r6=4
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x800000000000000
EOF2
RUN

NAME=rotld doubleword rotate left is 64-bit ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 78a43010 @ 0
aei
aeim
ar r5=0x8000000000000003
ar r6=4
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x00000038
EOF2
RUN

NAME=divdu is a 64-bit unsigned divide ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c853392 @ 0
aei
aeim
ar r5=0x8000000000000003
ar r6=4
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x2000000000000000
EOF2
RUN

NAME=lhax algebraic indexed load sign-extends ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 8001800280038004 @ 0x108
wx 7c8532ae @ 0
aei
aeim
ar r5=0x100
ar r6=8
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0xffffffffffff8001
EOF2
RUN

NAME=lwax algebraic indexed load sign-extends 32 bits ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 8001800280038004 @ 0x108
wx 7c8532aa @ 0
aei
aeim
ar r5=0x100
ar r6=8
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0xffffffff80018002
EOF2
RUN

NAME=lha D-form load halfword algebraic sign-extends without writeback ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 8001800280038004 @ 0x110
wx a8850010 @ 0
aei
aeim
ar r5=0x100
ar pc=0
s 0
aes
ar r4
ar r5
EOF2
EXPECT=<<EOF2
0xffffffffffff8001
0x00000100
EOF2
RUN

NAME=lwa D-form load word algebraic sign-extends ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 8001800280038004 @ 0x110
wx e8850012 @ 0
aei
aeim
ar r5=0x100
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0xffffffff80018002
EOF2
RUN

NAME=lhz D-form non-update load does not write back the base register ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 8001800280038004 @ 0x110
wx a0850010 @ 0
aei
aeim
ar r5=0x100
ar pc=0
s 0
aes
ar r4
ar r5
EOF2
EXPECT=<<EOF2
0x00008001
0x00000100
EOF2
RUN

NAME=lwarx load word and reserve uses both base and index registers ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c853028 @ 0
aoj 1 @ 0~{[0].esil}
EOF2
EXPECT=<<EOF2
r5,r6,+,[4],r4,=
EOF2
RUN

NAME=lwarx load word and reserve indexed execution ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 1122334455667788 @ 0x108
wx 7c853028 @ 0
aei
aeim
ar r5=0x100
ar r6=8
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x11223344
EOF2
RUN

NAME=ldarx load doubleword and reserve indexed execution ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 1122334455667788 @ 0x108
wx 7c8530a8 @ 0
aei
aeim
ar r5=0x100
ar r6=8
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x1122334455667788
EOF2
RUN

NAME=stwcx store word conditional uses both base and index registers ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c85312d @ 0
aoj 1 @ 0~{[0].esil}
EOF2
EXPECT=<<EOF2
r4,r5,r6,+,=[4]
EOF2
RUN

NAME=stwcx store word conditional indexed execution ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c85312d @ 0
aei
aeim
ar r4=0xaabbccddeeff0011
ar r5=0x100
ar r6=8
ar pc=0
s 0
aes
pv4 @ 0x108
EOF2
EXPECT=<<EOF2
0xeeff0011
EOF2
RUN

NAME=stdcx store doubleword conditional indexed execution ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7c8531ad @ 0
aei
aeim
ar r4=0xaabbccddeeff0011
ar r5=0x100
ar r6=8
ar pc=0
s 0
aes
pv8 @ 0x108
EOF2
EXPECT=<<EOF2
0xaabbccddeeff0011
EOF2
RUN

NAME=sld doubleword shift left of count >= 64 yields zero ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7ca43036 @ 0
aei
aeim
ar r5=0x8000000000000003
ar r6=65
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x00000000
EOF2
RUN

NAME=sld doubleword shift left count uses low 7 bits ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7ca43036 @ 0
aei
aeim
ar r5=0x8000000000000003
ar r6=128
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x8000000000000003
EOF2
RUN

NAME=srd doubleword shift right of count >= 64 yields zero ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 7ca43436 @ 0
aei
aeim
ar r5=0x8000000000000003
ar r6=64
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x00000000
EOF2
RUN

NAME=rlwinm wrapping mask fills the high word with the rotated value ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 54a42706 @ 0
aei
aeim
ar r5=0x12345678
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x2345678120000001
EOF2
RUN

NAME=rlwnm wrapping mask fills the high word with the rotated value ppc-64
FILE=malloc://0x200
CMDS=<<EOF2
e asm.arch=ppc
e asm.bits=64
e cfg.bigendian=true
wx 5ca43706 @ 0
aei
aeim
ar r5=0x12345678
ar r6=8
ar pc=0
s 0
aes
ar r4
EOF2
EXPECT=<<EOF2
0x3456781230000002
EOF2
RUN

NAME=addc carry-out ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7c853014 @ 0
aei
aeim
ar r5=0xffffffffffffffff
ar r6=2
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0x00000001
0x00000001
EOF
RUN

NAME=addc-adde 128-bit add carry chain ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7d253014 @ 0
wx 7c874114 @ 4
aei
aeim
ar r5=0xffffffffffffffff
ar r6=1
ar r7=0xffffffffffffffff
ar r8=0
aes
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0x00000000
0x00000001
EOF
RUN

NAME=subfc-subfe 128-bit subtract borrow chain ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7d253010 @ 0
wx 7c874110 @ 4
aei
aeim
ar r5=1
ar r6=5
ar r7=0x10
ar r8=0x40
aes
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0x00000030
0x00000001
EOF
RUN

NAME=addic carry-out ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 30850002 @ 0
aei
aeim
ar r5=0xffffffffffffffff
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0x00000001
0x00000001
EOF
RUN

NAME=subfic no-borrow sets carry ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 20850002 @ 0
aei
aeim
ar r5=1
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0x00000001
0x00000001
EOF
RUN

NAME=addze consumes carry-in ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7c870194 @ 0
aei
aeim
ar r7=0x100
ar ca=1
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0x00000101
0x00000000
EOF
RUN

NAME=addme consumes carry-in ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7c8701d4 @ 0
aei
aeim
ar r7=0x100
ar ca=1
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0x00000100
0x00000001
EOF
RUN

NAME=subfme consumes carry-in ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7c8701d0 @ 0
aei
aeim
ar r7=0x100
ar ca=1
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0xfffffffffffffeff
0x00000001
EOF
RUN

NAME=subfic borrow clears carry ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 20850002 @ 0
aei
aeim
ar r5=5
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0xfffffffffffffffd
0x00000000
EOF
RUN

NAME=subf does not touch carry ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7c853050 @ 0
aei
aeim
ar r5=2
ar r6=10
ar ca=1
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0x00000008
0x00000001
EOF
RUN

NAME=srawi sets carry from shifted-out sign bits ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7ca42670 @ 0
aei
aeim
ar r5=0xfffffffffffffff8
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0xffffffffffffffff
0x00000001
EOF
RUN

NAME=srawi on positive value clears carry ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7ca42670 @ 0
aei
aeim
ar r5=0x1f
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0x00000001
0x00000000
EOF
RUN

NAME=sraw register count sets carry ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7ca43630 @ 0
aei
aeim
ar r5=0xfffffffffffffff8
ar r6=4
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0xffffffffffffffff
0x00000001
EOF
RUN

NAME=sradi sets carry ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7ca4fe76 @ 0
aei
aeim
ar r5=0xfffffffffffffff0
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0xffffffffffffffff
0x00000001
EOF
RUN

NAME=addc carry-out with destination aliasing first operand ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7c632014 @ 0
aei
aeim
ar r3=0xffffffffffffffff
ar r4=2
aes
ar r3
ar ca
EOF
EXPECT=<<EOF
0x00000001
0x00000001
EOF
RUN

NAME=srad register count sets carry ppc-64
ARGS=-a ppc -e asm.bits=64 -e cfg.bigendian=true
FILE=malloc://0x100
CMDS=<<EOF
wx 7ca43634 @ 0
aei
aeim
ar r5=0xfffffffffffffff8
ar r6=4
aes
ar r4
ar ca
EOF
EXPECT=<<EOF
0xffffffffffffffff
0x00000001
EOF
RUN
